Phase Frequency Detector (PFD) Design with Frequency Dividers for a Phase Locked Loop (PLL) in 0.18-µm CMOS Technology

Abstract

This study presents a new CMOS dynamic Phase Frequency Detector design (PFD). The suggested PFD circuit (PPFD) has been developed, simulated, and the results have been examined. Internal signal routing is used in the PPFD circuit to reduce dead zone. A Loop-filter is nothing but the Low Pass Filter (LPF) integrates error current to generate VCO control voltage and suppresses the noise and unwanted phase detector outputs. Overall, the PLL is configured in 0.18 µm CMOS technology with a T-spice environment and it is then connected with the frequency divider circuits (FD/2 & FD 2/3). From the comparisons, it shows that the low power consumed is about 0.65 µW for the PLL with FD2/3. In addition, Monte Carlo simulation is performed for the PLL circuits and the power values are analyzed. In order to extend the research work, Pass transistor logic based FDs can be used to reduce power.