Hybrid Signed Digit Arithmetic in Efficient Computing: A Comparative Approach to Performance Assay

Abstract

In redundant representations, addition can be performed in a constant time independent of the word length of the operands. In practically all VLSI designs, the adder serves as a fundamental building element. The efficiency of a hybrid adder, which can add an unsigned number to a signed-digit number, determines the quality of the circuit's ultimate output. We designed and compared the speed of adders by reducing the carry propagation time using the combined effect of improved adder architectures and signed digit representation of number systems in this paper. The key concept is to find a balance between the execution time of the fast adding process and the available area, which is frequently very limited. We also attempted to verify the various algorithms of signed digit and hybrid signed digit adders in this paper.