The Design of a Static CMOS 16 Bit High Speed and Low Power Consumption Hybrid Adder Circuit Using Brent Kung Adder: A Recent Study

Abstract

In this research, a static sixteen Bit CMOS Brent kung adder structure was invented, which boasted a higher speed and reduced power consumption when compared to ripple deliver adders. The speed was improved by altering the shape and adding a Brent Kung adder, which uses (28 transistor, Boolean precise judgement) and is a lot faster than a ripple supply adder. These speed adders will help DSP processors grow. With the use of a 180nm Cadence device, time delays and power consumption are significantly reduced with unique adders.