Chaitanya KOMMU; A. Daisy RANI. The Mixed Logic Style based High-performance Binary Adder for ASIC Applications. Technological Innovation in Engineering Research Vol. 7, [S. l.], p. 26–40, 2022. DOI: 10.9734/bpi/tier/v7/7358F. Disponível em: https://stm.bookpi.org/TIER-V7/article/view/7917. Acesso em: 13 jun. 2026.