The Mixed Logic Style based High-performance Binary Adder for ASIC Applications - Chaitanya Kommu; A. Daisy Rani (Technological Innovation in Engineering Research Vol. 7, 2022)
The fundamental building blocks for creating data processing arithmetic units are binary adders. This paper presents a unique one-bit full adder that was created using Mixed Logic Design (MLS). The one-bit full adder is designed using a variety of logic topologies, including High-Skew (Hi-Skew), Low-Skew (Li-Skew), TGL (Transmission Gate Logic), and DVL (Dual Voltage Logic). The proposed design can reduce the number of transistors and switching activity. The circuit’s power and speed are modified by combining topologies and choosing the appropriate input signal to transfer. The H-SPICE simulation tool is used to evaluate the Full adder at different voltages. Hence the proposed MLS provides 83.53% less power consumption and a Propagation Delay of 14.02% at 0.8v.