N. K. Anushkannan and H. Mangalam. Phase Frequency Detector (PFD) Design with Frequency Dividers for a Phase Locked Loop (PLL) in 0.18-µm CMOS Technology. TIER-V3 [Internet]. 2022 Jun. 1 [cited 2026 Jun. 4];:28-43. Available from: https://stm.bookpi.org/TIER-V3/article/view/7058