J. Vijay Kumar and B. Nagaraju. Design and Development of CPLD Based on Low Power Pipelined 64-bit RISC Processor with Unbiased Floating Point Unit . TAER-V1 [Internet]. 2023 Nov. 21 [cited 2026 Jun. 23];:74-8. Available from: https://stm.bookpi.org/TAER-V1/article/view/12559