J. Vijay KUMAR; B. NAGARAJU. Design and Development of CPLD Based on Low Power Pipelined 64-bit RISC Processor with Unbiased Floating Point Unit . Theory and Applications of Engineering Research Vol. 1, [S. l.], p. 74–84, 2023. DOI: 10.9734/bpi/taer/v1/6884B. Disponível em: https://stm.bookpi.org/TAER-V1/article/view/12559. Acesso em: 23 jun. 2026.