Chaitanya KOMMU; A Daisy RANI. Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate. Science and Technology: Developments and Applications Vol. 5, [S. l.], p. 1–14, 2025. DOI: 10.9734/bpi/stda/v5/2365. Disponível em: https://stm.bookpi.org/STDA-V5/article/view/17160. Acesso em: 13 jun. 2026.