Real-Time FPGA Integration for Image Steganography Using Haar wavelet and Least Significant Bit Technique

Authors

  • Mangal Patil Department of ECE, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune, India.
  • Shankar Madkar Department of ECE, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune, India.
  • Jyoti Morbale Department of ECE, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune, India.
  • Harshal Hemane Department of ECE, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune, India.

DOI:

https://doi.org/10.9734/bpi/srnta/v6/2197

Keywords:

Wavelet transform, FPGA implementation, digital image steganography, least significant bit substitution, data security

Abstract

The purpose of this study is to develop a robust image steganography system that enhances the security of hidden communications by employing the Least Significant Bit (LSB) and Discrete Wavelet Transform (DWT) methods. The research aims to improve the robustness of the steganographic process and evaluate the effectiveness of these techniques. The study implements image steganography using two techniques: the Least Significant Bit (LSB) method and the Discrete Wavelet Transform (DWT) method. The performance of these algorithms is evaluated using key metrics such as Mean Squared Error (MSE), Bit Error Rate (BER), Peak Signal-to-Noise Ratio (PSNR), and processing time. The LSB method achieved PSNR values ranging from 42 to 46 dB and MSE values between 1.5 and 3.5. In contrast, the DWT method demonstrated superior performance, with PSNR values ranging from 49 to 57 dB and MSE values from 0.2 to 0.7. These results indicate that the DWT method provides higher performance and robustness compared to the LSB technique. The Discrete Wavelet Transform (DWT) method outperforms the Least Significant Bit (LSB) technique, offering better PSNR and lower MSE values. This makes DWT a more robust and efficient solution for image steganography, particularly in scenarios requiring high security and minimal image distortion.

Published

2024-10-31

How to Cite

Mangal Patil, Shankar Madkar, Jyoti Morbale, & Harshal Hemane. (2024). Real-Time FPGA Integration for Image Steganography Using Haar wavelet and Least Significant Bit Technique. Scientific Research, New Technologies and Applications Vol. 6, 30–51. https://doi.org/10.9734/bpi/srnta/v6/2197