Analytical Methods for Detecting and Eliminating the Static Hazard in Combinational Logic Circuits

Abstract

A logic glitch is a kind of unwanted noise, its presence in the output signal can initiate an uncontrollable process, in the next level which is an input signal. There can be distinguished three types of noise that are introduced in (CLC) Combinational Logic Circuits, called hazards (Static, Dynamic and Function Hazards). In this paper, the authors continue the research that consists of a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of POS – Product of Sums, static hazard “0”.

In the first method it’s used the consensus theorem to determine the cover term that is equal to the product of the two residual implicants, and in the second method, it’s resolved a Boolean equation system. The authors observed that in the second method, the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.