Recent Analysis of NAND Gate Based Phase Frequency Detector for Phase Locked Loop (PLL)

Abstract

Phase Locked Loop (PLL) must operate at higher frequencies as RF IC technology advances, but low power consumption is also necessary. PLL is an indispensable element of electronic industry. Proposed Phase frequency detector (PFD) design employing a NAND gate that consumes significantly less power while also taking into account different parameters such as rise time and slew rate over temperature variations. At \(65^{\circ}\)c, the slew rate varies from 44 to 30 v/ns, and the rise time varies from 23 to 56 ps.