Murty, M. N., S. S. Nayak, Binayak Padhy, and S.N. Panda. “Study on Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier”. Novel Perspectives of Engineering Research Vol. 7 (February 14, 2022): 110–116. Accessed June 4, 2026. https://stm.bookpi.org/NPER-V7/article/view/5907.