M. N. MURTY; S. S. NAYAK; Binayak PADHY; S.N. PANDA. Study on Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier. Novel Perspectives of Engineering Research Vol. 7, [S. l.], p. 110–116, 2022. DOI: 10.9734/bpi/nper/v7/1676B. Disponível em: https://stm.bookpi.org/NPER-V7/article/view/5907. Acesso em: 4 jun. 2026.