Dhanabalan .; Tamil SELVI. Implementation of High Speed 8-bit Multiplier in FPGA with Lesser Adder Elements. Novel Perspectives of Engineering Research Vol. 7, [S. l.], p. 80–87, 2022. DOI: 10.9734/bpi/nper/v7/1763B. Disponível em: https://stm.bookpi.org/NPER-V7/article/view/5904. Acesso em: 4 jun. 2026.