Veena Sanath Kumar, Abhishek L S, Chandu H M, Chirag A and Rohan S. Design of Low Power Configurable Multiclock Digital System from RTL to GDSII. ISASATWF [Internet]. 2025 Feb. 10 [cited 2026 Jul. 28];:171-80. Available from: https://stm.bookpi.org/ISASATWF/article/view/17224