Generalised Space Vector Pulse Width Modulation Method for Multilevel Inverters Including over Modulation Region and Its Implementation with FPGA

Authors

  • B. Sirisha Department of EEE, University College of Engineering Osmania University, Hyderabad, India.

DOI:

https://doi.org/10.9734/bpi/mono/978-93-5547-725-5

Keywords:

Multilevel inverter, electronic topologies, lesser harmonic distortion, FPGA processor

Abstract

Multilevel power converters are power electronic topologies for high power motor drive applications and utility applications requiring medium voltage and megawatt level, because of its low Electromagnetic Interference and high efficiency, These inverters can solve the problems associated with traditional two level inverters. Even though number of Pulse Width Modulation strategies are available for switching the multilevel inverters (such as multi carrier, inter leaved strategies and sigma-delta) unfortunately these strategies could not meet the required standards of modern drives. Therefore compared to various other modulation techniques, Space Vector Pulse Width Modulation is the predominant one which offers better DC link utilization, lesser harmonic distortion.

The main requirement of any drive is implementation feasibility, as it is not only concerned with cost and also imitating the theoretical performance in real time as faithfully as possible. This book presents generalized SVPWM algorithm for any level inverter. In SVPWM the abrogation of output voltage limit is possible through over modulation. The over modulation is indispensable, as the extended speed- torque and power characteristics of the drive are desired. The over modulation in SVPWM   controlled Multilevel inverter is not straight forward one and possesses many challenges , No work has been reported on the operation of  generalized  SVPWM  algorithm for any level inverter which offers distinguished research scopes. Due to the nature and performance boundaries, the over modulation region has been divided into OVM-I and OVM-II. The trajectory of the voltage reference in over modulation is a mixture of circular and hexagonal boundary and breeds as a piece wise continuous function. The over modulation strategy for SVPWM   is very complex and hybrid in nature incorporating both under modulation and over modulation algorithms. Host PWM techniques of SVPWM in over modulation in typical dual-mode strategy, typical single-mode strategy, minimum phase angle error strategy and minimum amplitude strategies have been noticed for both Cascaded H-Bridge and Diode Clamped Inverters. The majority of PWM strategies for over modulation are complex which requires complex optimization techniques with solution to nonlinear equations and memory lookup table requirement and are limited  upth three level only. This generalized SVPWM technique is impleted for both Cascaded and Diode Clamped multilevel inverters including over modulation region. To work for its completeness, this method is  implemented experimentally using SPARTAN 3A FPGA processor by  testing for five, seven level Cascaded Inverters and  seven level Diode Clamped Multilevel Inverter with Induction motor load .

The performance of inverter is analyzed in terms of voltage, current THD and magnitude of fundamental line voltage including the over modulation region is investigated. Thus minimizing the filter size requirement of the inverter, employed in industrial applications. Where sinusoidal output voltage is required.

As a whole, apart from the FPGA implementation of MLI-SVPWM, this book provides a generalized SVPWM algorithm including over modulation with generalized on line switching schemes, utilizing the desired and redundant switching states for reduction of THD.

Published

2022-07-13

How to Cite

B. Sirisha. (2022). Generalised Space Vector Pulse Width Modulation Method for Multilevel Inverters Including over Modulation Region and Its Implementation with FPGA. Generalised Space Vector Pulse Width Modulation Method for Multilevel Inverters Including over Modulation Region and Its Implementation With FPGA, 1–157. https://doi.org/10.9734/bpi/mono/978-93-5547-725-5