Machine-Learning-Based Compact Modeling and Model Parameter Extraction for Sub-3-nm-Node Emerging Transistors

Abstract

In this paper, we present an artificial neural network (ANN)-based compact model for evaluating the characteristics of nanosheet field-effect transistors (NSFETs), a promising next-generation nano-device. Using the Sentaurus TCAD simulator,  data was extracted that accurately reflects the physical characteristics of NSFETs. The ANN model, implemented in Verilog-A, predicts device currents and capacitances with high accuracy and efficiency using five key geometric parameters and two voltage biases. Extensive experiments demonstrate for the first time that the proposed model is several times faster and more accurate than existing compact models, significantly reducing compact model development, model parameter extraction, and circuit simulation time while maintaining high precision. This advancement has the potential to accelerate the design of sub-3-nm transistors, thereby lowering development costs and time. In particular, while the industry standard compact model typically requires 7-8 weeks to extract SPICE model parameters for a designed device, the proposed ANN-based compact modeling approach can provide a SPICE model within a day. Moreover, even in the absence of physics-based compact model development for next-generation semiconductors, this data-driven ANN-based compact modeling approach offers a less technology-dependent solution, providing real-time SPICE models for circuit simulations. Future work will explore the application of this model to other emerging transistor technologies, the further optimization of simulation speed and accuracy, and design technology co-optimization (DTCO) capabilities.